A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
Periphery transistors include metal-oxide semiconductor field effect transistors (MOSFETs) that, amongst other capabilities, control charging and discharging individual memory cells in the flash memory. The charging and discharging of the memory cells allow for the appropriate reading and writing of data to the specific memory cells in the flash memory. In one application, the periphery transistors can be high voltage transistors that are used to block high voltages (e.g., 20 volts) needed to run devices containing the flash memory.
As flash memory technology progresses, emphasis is directed to reduce the size of the memory cells in the flash memory and the periphery transistors supporting the flash memory. This is an effort to reduce the overall size of the chip.
Prior Art FIG. 1 is a diagram of a typical MOSFET transistor 100 that can be utilized as a periphery transistor in support of a flash memory. Prior Art FIG. 1 illustrates the negative effects of punch-through especially during application of higher voltages (e.g., 20 volts) due to reduced gate lengths. The MOSFET 100 includes a substrate 110 that includes a source region 140 and a drain region 170 that is separated by an underlying channel region under the stacked gate structure 120. The MOSFET transistor includes a lightly doped source region 130 and a lightly doped drain (LDD) region 160, both referred to as LDD regions.
However, continued reduction in size of the gate length of periphery transistors has been limited by short channel effects. Specifically, the behavior of the transistor is negatively governed by punch-through of electrons at the higher voltages. When the effective channel length between the LDD region 130 and the LDD region 160 becomes too short, the depletion region under the gate stack 120 is formed partly by the bias voltage on the drain region 170 and the built-in potential of the source region 140. As a result, the depletion region 180 due to a high bias voltage (e.g., 20 volts) on the drain region 170 can extend to the depletion region 150 surrounding the source region 140.
Correspondingly, the barrier for electron injection from the source region 140 to the drain region 170 decreases due to the extension of the depletion region 180. Specifically, at high positive drain voltages, the effective energy barrier height for electrons is reduced and electrons can migrate from the source region 140 to the drain region 170. This is known as drain induced barrier lowering (DIBL).
In the worst case, when the depletion regions 180 and 150 touch each other punch-through will occur. This will result in loss of gate control over the channel, and result in significant current flow from the source 140 to the drain 170.
Thus, even when the MOSFET 100 is turned off by biasing the stacked gate to zero volts, for high voltages (e.g., 20 volts) that are applied to the drain region 170, an unwanted current flows from the source region 140 to the drain region 170 due to punch-through. This in turn reduces the breakdown voltage of the MOSFET 100.